This invention relates generally to voltage regulators and, in particular, to methods of reducing the quiescent current of voltage regulators. Voltage regulators, such as DC-to-DC converters, are used to provide stable voltage sources for electronic systems. Efficient DC-to-DC converters are particularly needed to extend battery run-time in low-power devices, such as mobile phones and hand-held computers.
Such devices impose a wide range of load current requirements upon voltage regulators. For example, the current requirements of a digital baseband or embedded processor load may reach several hundred milliamperes during an active state, such as a talk mode or compute mode, only to be throttled down to tens or units of microamperes during an idle mode. An important fraction of the device""s energy may be consumed during this idle mode.
In general, in one aspect, the invention features a method, apparatus, and computer program product for use within a voltage regulator. It includes deactivating the voltage regulator; and periodically activating the voltage regulator to monitor and selectively refresh the output of the voltage regulator.
Particular implementations can include one or more of the following features. The voltage regulator includes active elements and inactive elements, and deactivating includes eliminating quiescent current in at least one of the active elements. Periodically activating includes periodically restoring quiescent current in at least one of the active elements. Restoring includes restoring quiescent current in an output monitor configured to monitor the output level of the voltage regulator. The output monitor asserts a refresh signal when the level of the output of the voltage regulator deviates from a predetermined range, and the invention further includes restoring quiescent current in a pulse generator when the monitor asserts the refresh signal, thereby refreshing the output of the voltage regulator. The output monitor receives a predetermined reference voltage from a reference voltage generator, and restoring further includes restoring quiescent current in the reference voltage generator. Deactivating includes deactivating the voltage regulator when an ultra-low-power mode input signal is detected. Periodically activating includes repeatedly activating the voltage regulator based on a periodic signal. Periodically activating further includes receiving the periodic signal; waiting for a predetermined number of cycles of the periodic signal; and activating the voltage regulator after waiting.
In general, in another aspect, the invention features a controller for use within a voltage regulator. It includes a timer configured to assert a periodic check signal; and a logic module configured to deactivate the voltage regulator and to thereafter periodically activate the voltage regulator to monitor and selectively refresh the output of the voltage regulator in response to the check signal.
Particular implementations can include one or more of the following features. It includes an output monitor configured to monitor the output level of the voltage regulator when the logic module asserts a monitor enable signal, and to shut down when the logic module does not assert the monitor enable signal. The output monitor is configured to assert a refresh signal when the level of the output of the voltage regulator deviates from a predetermined range and the monitor enable signal is asserted; and the logic module is configured to assert a pulse enable signal when the refresh signal is asserted. The invention includes a pulse generator configured to cause the voltage regulator to refresh the output of the voltage regulator when the refresh signal and pulse enable signals are asserted. The invention includes a reference voltage generator configured to supply a predetermined reference voltage to the output monitor. The timer includes a counter configured to assert the check signal every n cycles of a clock signal, where n is programmable. The timer is configured to assert the check signal when an ultra-low-power mode signal is asserted. The clock signal is external to the controller. The invention includes a clock generator configured to provide the clock signal. The voltage regulator has a buck topology and the counter is powered by the output of the regulator. The voltage regulator has a boost topology and the counter is powered by the input to the regulator.
In general, in yet another aspect, the invention features a voltage regulator. It includes a timer configured to assert a periodic check signal; and a logic module configured to deactivate the voltage regulator and to thereafter periodically activate the voltage regulator to monitor and selectively refresh the output of the voltage regulator in response to the check signal.
Particular implementations can include one or more of the following features. The invention includes an output monitor configured to monitor the output level of the voltage regulator when the logic module asserts a monitor enable signal, and to shut down when the logic module does not assert the monitor enable signal. The output monitor is configured to assert a refresh signal when the level of the output of the voltage regulator deviates from a predetermined range and the monitor enable signal is asserted; and the logic module is configured to assert a pulse enable signal when the refresh signal is asserted. The invention includes a pulse generator configured to cause the voltage regulator to refresh the output of the voltage regulator when the refresh signal and pulse enable signals are asserted.
Advantages that can be seen in implementations of the invention include the following. Use of embodiments of the present invention can result in a reduction in the quiescent current of the switching regulator and a significant increase in battery standby time for portable devices.